The present invention generally relates to semiconductor devices and more particularly to a semiconductor memory device such as a dynamic random access memory in which power conductor patterns are provided for selectively activating sense amplifiers that are provided in a memory cell array in correspondence to memory cell columns.
In large capacity semiconductor memories such as DRAMs that have a very large storage capacity of information, a very large number of memory cells are activated in response to single row address data or RAS access. In such large capacity memories, therefore, a very large number of bit lines are charged or discharged in response to a single RAS access, and the delay associated with such charging and discharging of the bit lines has become a major factor that impedes high speed operation of the memory device.
In order to attend to this problem, various proposals are made so far. For example, one may reduce the number of the memory cells that are activated by a single row address, by dividing a memory cell block into a plurality of sub-blocks. However, such an approach invites an increase in the chip size and hence the cost of the device.
Another approach to this problem is to provide a large driving power to sense amplifiers that cause charging and discharging of the bit lines. In relation to this, there arises a demand for minimizing the resistance of power conductor patterns that are used for feeding drive current to the respective sense amplifiers.
In order to meet the demand of reduced resistance of the power conductor patterns, recent semiconductor memory devices use a layout in which each of the sense amplifiers that are driven by a driver circuit is disposed in the vicinity of the driver circuit. Conversely, the driver circuits are disposed in the vicinity of the sense amplifiers that cooperate therewith. By constructing the semiconductor memory device as such, it becomes possible to reduce the length and hence the resistance of the power conductor pattern.
In such conventional DRAMs, a power conductor pattern inevitably extends parallel with a signal conductor pattern used for conducting a selection of sense amplifiers, and the power conductor patterns and the signal conductor patterns are formed to extend parallel with each other on the same wiring layer covering the memory cell array. It will be understood that such a construction is vulnerable to dusts that may cause a short circuit between the power conductor pattern and the adjacent signal conductor pattern.
FIG. 1 shows the construction of a conventional DRAM in which drivers of the sense amplifiers are distributed in the memory cell array for reducing the length of the power conductor patterns leading therefrom to the sense amplifiers.
Referring to FIG. 1, the DRAM is formed on a chip 1 in which memory cell blocks 2.sub.-1 -2.sub.-8, 3.sub.-1 -3.sub.-8, 4.sub.-1, 4.sub.-2, 5.sub.-1, 5.sub.-2, . . . are provided, wherein each of the memory cell blocks 2.sub.-1 -2.sub.-8, 3.sub.-1 -3.sub.-8, 4.sub.-1, 4.sub.-2, 5.sub.-1, 5.sub.-2, . . . includes an array of memory cells in which memory cells are arranged in rows and columns. Further, the chip 1 carries thereon a plurality of sense amplifier blocks 6.sub.-1 -6.sub.-4, 7.sub.-1 -7.sub.-4, 8.sub.-1, 9.sub.-1 . . . , wherein each of the sense amplifier blocks includes a number of sense amplifiers arranged in a row, together with a driver circuit. By selecting one of the sense amplifiers in a sense amplifier block, a group of memory cells aligned in a column are selected in the corresponding memory cell block.
Further, the chip 1 carries thereon row decoders 10.sub.-1 -10.sub.-8, 11.sub.-1 -11.sub.-8, 12.sub.-1, 12.sub.-2, 13.sub.-1, 13.sub.-2, . . . , wherein the row decoders decode row address data supplied thereto and select a word line corresponding to the supplied address data as usual in DRAMs. Similarly, the chip 1 carries thereon column decoders 14-17 wherein the column decoders decode column address data supplied thereto and produce a column selection signal in response thereto for selecting a sense amplifier that is provided in each column.
In relation to the selection of the sense amplifiers, the chip 1 carries thereon signal conductor patterns 18.sub.-1 -18.sub.-4, 19.sub.-1 -19.sub.-4, 20.sub.-1 -20.sub.-4, and 21.sub.-1 -21.sub.-4 for carrying column selection signals, such that the signal conductor patterns extend from the column decoders 14-17 to the corresponding sense amplifiers for supplying the column selection signals thereto. Further, the chip 1 carries thereon an electrode pad 22 for a Vcc voltage, wherein the Vcc voltage is distributed from the pad 22 to various parts of the semiconductor integrated circuit on the chip 1 by way of power conductor patterns 23-26 as well as power conductor patterns 27.sub.-7, 27.sub.-2, 28.sub.-1, 28.sub.-2, 29.sub.-1, 29.sub.-2, 30.sub.-1, 30.sub.-2. It should be noted that the power conductor patterns 27.sub.-1, 27.sub.-2, 28.sub.-1, 28.sub.-2, 29.sub.-1, 29.sub.-2, 30.sub.-1 and 30.sub.-2 are used explicitly for supplying the Vcc voltage to driver circuits of the sense amplifiers.
Similarly to the Vcc pad 22, the chip 1 carries thereon an electrode pad 31 for a Vss voltage, wherein the Vcc voltage is distributed from the pad 31 to various parts of the semiconductor integrated circuit on the chip 1 by way of power conductor patterns 32-35 as well as by way of power conductor patterns 36.sub.-1, 36.sub.-2, 37.sub.-1, 37.sub.-2, 38.sub.-1, 38.sub.-2, 39.sub.-1 and 39.sub.-2, wherein the power conductor patterns 36.sub.-1, 36.sub.-2, 37.sub.-1, 37.sub.-2, 38.sub.-1, 38.sub.-2, 39.sub.-1 and 39.sub.-2 are used explicitly for supplying the Vss voltage to the driver circuits of the sense amplifiers, in addition to the Vcc voltage mentioned previously.
FIG. 2 shows a part of the drawing of FIG. 1 that includes the conductor patterns 18.sub.-1 -18.sub.-4, 27.sub.-1 -27.sub.-2 and 36.sub.-1 -36.sub.-2, in a cross sectional view taken along a line X--X' shown in FIG. 1.
Referring to FIG. 2, it will be noted that the conductor patterns 18.sub.-1 -18.sub.-4, 27.sub.-1 -27.sub.-2 and 36.sub.-1 -36.sub.-2 extend parallel with each other in a column direction on the principal surface of the chip 1, wherein each of the conductor patterns 18.sub.-1 -18.sub.-4 is laterally bounded by a power conductor pattern that carries the Vcc voltage such as a pattern 27.sub.-1 at a first side and further by a power conductor pattern that carries the Vss voltage such as a pattern 36.sub.-1 at the other side.
In the semiconductor integrated circuit having such a construction, it will be noted that a dust particle having a size sufficient to cause a bridging across a pair of adjacent conductor patterns may easily cause a short circuit between the signal conductor pattern and the power conductor pattern. For example, a dust particle having a size A may cause a short circuit between the conductor patterns 18.sub.-1 and 27.sub.-1 or between the conductor patterns 18.sub.-4 and 36.sub.-2. Similarly, a dust particle having a size B may cause a short circuit between the conductor patterns 36.sub.-1 and 27.sub.-2 across the conductor pattern 18.sub.-3.
As long as the short circuit occurs between a power conductor pattern that carries the Vss voltage and a signal conductor pattern, no substantial problem occurs. It should be noted that the signal conductor pattern is in the Vss level at the time of stand-by operational mode, and no substantial current flows between the signal conductor pattern and the power conductor pattern having the Vss level.
On the other hand, when a short circuit occurs between the signal conductor pattern and the power conductor pattern that carries the Vcc voltage, a current is caused to flow from the power conductor pattern to the signal conductor pattern even at the time of stand-by mode, via the dust particle bridging thereacross. Further, when a dust particle having the size B causes a short circuit across the power conductor pattern that carries the Vss voltage and the power conductor pattern that carries the Vcc voltage, a current flows inevitably from the power conductor pattern at the Vcc level to the signal conductor pattern intervening between the two power conductor patterns at the time of the stand-by mode.
As the specification of DRAMs allows only a very small leak current in the stand-by mode, such a short circuit including the power conductor pattern of the Vcc voltage level generally renders the device as being defective, even when the short circuit is a minor one.
A short circuit between the power conductor pattern of the Vss level and the signal conductor pattern may also cause a problem in that the voltage level of the signal conductor pattern does not rise in the active operation mode, particularly in the case where the degree of short-circuit is substantial. In such a case, however, the defect may be saved by selecting a redundant memory cell column in place of the defective memory cell column in which the short circuit has occurred. In other words, the problem of short circuit of the signal conductor pattern may be saved by using the redundancy of the DRAM, as long as the short circuit occurs between the signal conductor pattern and the power conductor pattern of the Vss level.
On the contrary, the short circuit between the signal conductor pattern and the power conductor pattern of the Vcc level cannot be saved by the redundancy. It should be noted that the defective column maintains the selected state as a result of the short circuit, even when a redundant column is selected by way of the redundant construction. In such a case, a multiple accessing occurs in the DRAM in response to single address data. The same situation occurs also in the case where a power conductor pattern of the Vcc level and a power conductor patter of the Vss level are bridged by the dust particle having the size B. Hereinafter, the short circuit that causes a problem that cannot be saved by redundancy will be designated as "harmful short circuit."